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1. general description the hef4013b-q100 is a dual d-type flip-flop that features independe nt set-direct input (sd), clear-direct input (cd), clock input (cp) and outputs (q, q ). data is accepted when cp is low and is transferred to the output on the positive-going edge of the clock. the active high asynchronous cd and sd inputs are independent and override the d or cp inputs. the outputs are buffered for best syste m performance. the schmitt trigger action of the clock inputs, makes the circuit highly tolerant of slower clock rise and fall times. it operates over a recommended v dd power supply range of 3 v to 15 v referenced to v ss (usually ground). connect unused inputs to v dd , v ss , or another input. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? tolerant of slow clock rise and fall times ? fully static operation ? 5 v, 10 v, and 15 v parametric ratings ? standardized symmetrical output characteristics ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? complies with jedec standard jesd 13-b 3. applications ? counters and dividers ? registers ? toggle flip-flops hef4013b-q100 dual d-type flip-flop rev. 2 ? 20 february 2013 product data sheet
hef4013b_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 20 february 2013 2 of 16 nxp semiconductors hef4013b-q100 dual d-type flip-flop 4. ordering information 5. functional diagram table 1. ordering information all types operate from ? 40 ? c to +125 ? c type number package name description version HEF4013BP-Q100 dip14 plastic dual in- line package; 14 leads (300 mil) sot27-1 hef4013bt-q100 so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 hef4013btt-q100 tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 fig 1. functional diagram 001aag084 1sd 1d 1cp 1cd 2sd 2d 2q 2q 1q 1q 13 12 1 2 2cp 2cd 6 5 3 4 8 9 11 10 sd cd dq ff1 cp q sd cd dq ff2 cp q
hef4013b_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 20 february 2013 3 of 16 nxp semiconductors hef4013b-q100 dual d-type flip-flop 6. pinning information 6.1 pinning 6.2 pin description fig 2. logic diagram (one flip-flop) d sd cd cp c c 001aag086 c c c c c c c c q q fig 3. pin configuration

table 2. pin description symbol pin description 1q, 2q 1, 13 true output 1q , 2q 2, 12 complement output 1cp, 2cp 3, 11 clock input (l ow to high edge-triggered)
hef4013b_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 20 february 2013 4 of 16 nxp semiconductors hef4013b-q100 dual d-type flip-flop 7. functional description [1] h = high voltage level; l = low voltage level; x = don?t care; ?? = low-to-high clock transition. 8. limiting values [1] for dip14 packages: above t amb = 70 ? c, p tot derates linearly with 12 mw/k. [2] for so14 packages: above t amb = 70 ? c, p tot derates linearly with 8 mw/k. [3] for tssop14 packages: above t amb = 60 ? c, p tot derates linearly with 5.5 mw/k. 1cd, 2cd 4, 10 asynchronous clear-direct input (active high) 1d, 2d 5, 9 data input 1sd, 2sd 6, 8 asynchronous set-direct input (active high) v ss 7 ground (0 v) v dd 14 supply voltage table 2. pin description ?continued symbol pin description table 3. function table [1] control input output nsd ncd ncp nd nq nq hl xxhl l hxxl h hhxxhh ll? llh ll? hhl table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to v ss = 0 v (ground). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +18 v i ik input clamping current v i < ? 0.5 v or v i >v dd + 0.5 v - ? 10 ma v i input voltage ? 0.5 v dd + 0.5 v i ok output clamping current v o < ? 0.5 v or v o >v dd + 0.5 v - ? 10 ma i i/o input/output current - ? 10 ma i dd supply current - 50 ma t stg storage temperature ? 65 +150 ?c t amb ambient temperature ? 40 +125 ?c p tot total power dissipation t amb = ? 40 ? c to +125 ?c dip14 [1] - 750 mw so14 [2] - 500 mw tssop14 [3] - 500 mw p power dissipation per output - 100 mw
hef4013b_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 20 february 2013 5 of 16 nxp semiconductors hef4013b-q100 dual d-type flip-flop 9. recommended operating conditions 10. static characteristics table 5. recommended operating conditions symbol parameter conditions min max unit v dd supply voltage 3 15 v v i input voltage 0 v dd v t amb ambient temperature ? 40 +125 ?c ? t/ ? v input transition rise and fall rate v dd = 5 v - 3.75 ? s/v v dd = 10 v - 0.5 ? s/v v dd = 15 v - 0.08 ? s/v table 6. static characteristics v ss = 0 v; v i =v ss or v dd ; unless otherwise specified. symbol parameter conditions v dd t amb = ? 40 ?c t amb = +25 ?c t amb = +85 ?c t amb = +125 ?c unit min max min max min max min max v ih high-level input voltage ?i o ? < 1 ? a 5 v 3.5 - 3.5 - 3.5 - 3.5 - v 10 v 7.0 - 7.0 - 7.0 - 7.0 - v 15 v 11.0 - 11.0 - 11.0 - 11.0 - v v il low-level input voltage ?i o ? < 1 ? a 5 v - 1.5 - 1.5 - 1.5 - 1.5 v 10 v - 3.0 - 3.0 - 3.0 - 3.0 v 15 v - 4.0 - 4.0 - 4.0 - 4.0 v v oh high-level output voltage ?i o ? < 1 ? a 5 v 4.95 - 4.95 - 4.95 - 4.95 - v 10 v 9.95 - 9.95 - 9.95 - 9.95 - v 15 v 14.95 - 14.95 - 14.95 - 14.95 - v v ol low-level output voltage ?i o ? < 1 ? a 5 v - 0.05 - 0.05 - 0.05 - 0.05 v 10 v - 0.05 - 0.05 - 0.05 - 0.05 v 15 v - 0.05 - 0.05 - 0.05 - 0.05 v i oh high-level output current v o = 2.5v 5v - ? 1.7 - ? 1.4 - ? 1.1 - ? 1.1 ma v o = 4.6 v 5 v - ? 0.64 - ? 0.5 - ? 0.36 - ? 0.36 ma v o = 9.5 v 10 v - ? 1.6 - ? 1.3 - ? 0.9 - ? 0.9 ma v o = 13.5 v 15 v - ? 4.2 - ? 3.4 - ? 2.4 - ? 2.4 ma i ol low-level output current v o = 0.4 v 5 v 0.64 - 0.5 - 0.36 - 0.36 - ma v o = 0.5 v 10 v 1.6 - 1.3 - 0.9 - 0.9 - ma v o = 1.5 v 15 v 4.2 - 3.4 - 2.4 - 2.4 - ma i i input leakage current 15 v - ? 0.1 - ? 0.1 - ? 1.0 - ? 1.0 ? a i dd supply current all valid input combinations; ?i o ? =0 a 5 v - 1.0 - 1.0 - 30 - 30 ? a 10 v - 2.0 - 2.0 - 60 - 60 ? a 15 v - 4.0 - 4.0 - 120 - 120 ? a c i input capacitance - ---7.5-- - -pf
hef4013b_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 20 february 2013 6 of 16 nxp semiconductors hef4013b-q100 dual d-type flip-flop 11. dynamic characteristics table 7. dynamic characteristics t amb = 25 ? c; unless otherwise specifie d. for test circuit see figure 6 . symbol parameter conditions v dd extrapolation formula min typ max unit t phl high to low propagation delay ncp to nq, nq ; see figure 4 5 v [1] 83 + 0.55 ? c l - 110 220 ns 10 v 34 + 0.23 ? c l - 4590ns 15 v 22 + 0.16 ? c l - 3060ns nsd to nq 5 v [1] 73 + 0.55 ? c l - 100 200 ns 10 v 29 + 0.23 ? c l - 4080ns 15 v 22 + 0.16 ? c l - 3060ns ncd to nq 5 v [1] 73 + 0.55 ? c l - 100 200 ns 10 v 29 + 0.23 ? c l - 4080ns 15 v 22 + 0.16 ? c l - 3060ns t plh low to high propagation delay ncp to nq, nq ; see figure 4 5 v [1] 68 + 0.55 ? c l -95190ns 10 v 29 + 0.23 ? c l - 4080ns 15 v 22 + 0.16 ? c l - 3060ns nsd to nq 5 v [1] 48 + 0.55 ? c l -75150ns 10 v 24 + 0.23 ? c l - 3570ns 15 v 17 + 0.16 ? c l - 2550ns ncd to nq 5 v [1] 33 + 0.55 ? c l -60120ns 10 v 19 + 0.23 ? c l - 3060ns 15 v 12 + 0.16 ? c l - 2040ns t t transition time see figure 4 5 v [1] 10 + 1.00 ? c l -60120ns 10 v 9 + 0.42 ? c l - 3060ns 15 v 6 + 0.28 ? c l - 2040ns t su set-up time nd to ncp; see figure 4 5 v 40 20 - ns 10 v 25 10 - ns 15 v 15 5 - ns t h hold time nd to ncp; see figure 4 5 v 20 0 - ns 10 v 20 0 - ns 15 v 15 0 - ns t w pulse width ncp input low; see figure 4 5 v 60 30 - ns 10 v 30 15 - ns 15 v 20 10 - ns nsd input high; see figure 5 5 v 50 25 - ns 10 v 24 12 - ns 15 v 20 10 - ns ncd input high; see figure 5 5 v 50 25 - ns 10 v 24 12 - ns 15 v 20 10 - ns
hef4013b_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 20 february 2013 7 of 16 nxp semiconductors hef4013b-q100 dual d-type flip-flop [1] typical values of the propagation delays and output transition times can be calculated with the extrapolation formulas. c l is given in pf. 12. waveforms t rec recovery time nsd input; see figure 5 5 v +15 ? 5- ns 10 v 15 0 - ns 15 v 15 0 - ns ncd input; see figure 5 5 v 40 25 - ns 10 v 25 10 - ns 15 v 25 10 - ns f clk(max) maximum clock frequency see figure 4 5 v 7 14 - mhz 10 v 14 28 - mhz 15 v 20 40 - mhz table 7. dynamic characteristics ?continued t amb = 25 ? c; unless otherwise specifie d. for test circuit see figure 6 . symbol parameter conditions v dd extrapolation formula min typ max unit table 8. dynamic power dissipation v ss = 0 v; t r = t f ? 20 ns; t amb = 25 ? c. symbol parameter v dd typical formula where p d dynamic power dissipation 5 v p d = 850 ? f i + ? (f o ? c l ) ? v dd 2 ? wf i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; ? (f o ? c l ) = sum of the outputs; v dd = supply voltage in v. 10 v p d = 3600 ? f i + ? (f o ? c l ) ? v dd 2 ? w 15 v p d = 9000 ? f i + ? (f o ? c l ) ? v dd 2 ? w set-up and hold times are shown as positive values but may be specified as negative values. the shaded areas indicate when the input is per mitted to change for predictable output performance. measurement points are given in table 9 . fig 4. set-up time, hold time, minimum clock pulse width, propagation delays and transition times 001aah016 0 v 0 v t h t su 1/f clk(max) t h t su t f t r t w v m v m v m v i v oh v ol v i output nq input ncp input nd t t t t t phl t plh v y v x
hef4013b_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 20 february 2013 8 of 16 nxp semiconductors hef4013b-q100 dual d-type flip-flop recovery times are shown as positive values but may be specified as negative values. measurement points are given in table 9 . fig 5. nsd, ncd recovery time and pulse width 001aag088 input nsd input ncd input ncp v i 0 v 0 v v ol 0 v v i v i v oh t w v m t w v m v m output nq t rec t rec table 9. measurement points supply voltage input output v dd v m v m v x v y 5 v to 15 v 0.5v dd 0.5v dd 0.1v dd 0.9v dd test and measurement data is given in ta b l e 1 0 ; definitions test circuit: dut = device under test. r t = termination resistance should be equal to output impedance z o of the pulse generator. c l = load capacitance including jig and probe capacitance. fig 6. test circuit for measuring switching times v dd v i v o 001aag182 dut c l r t g table 10. test data supply voltage input load v dd v i t r , t f c l 5 v to 15 v v ss or v dd ? 20 ns 50 pf
hef4013b_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 20 february 2013 9 of 16 nxp semiconductors hef4013b-q100 dual d-type flip-flop 13. application information fig 7. n-stage shift register fig 8. binary ripple up-counter; divide-by-2 n fig 9. modified ring counter; divide-by-(n + 1) 001aag089 cp ff 1 q q d dq clock cp ff 2 q q d cp ff n q q d 001aag090 cp t-type flip-flop ff 1 q q dq clock cp ff 2 q q d cp ff n q q d 001aag091 cp ff 1 q q dq clock cp ff 2 q q d cp ff n q q d
hef4013b_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 20 february 2013 10 of 16 nxp semiconductors hef4013b-q100 dual d-type flip-flop 14. package outline fig 10. package outline sot27-1 (dip14) unit a max. 1 2 (1) (1) b 1 cd (1) z ee m h l references outline version european projection issue date iec jedec jeita mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot27-1 99-12-27 03-02-13 a min. a max. b max. w m e e 1 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 2.2 4.2 0.51 3.2 0.068 0.044 0.021 0.015 0.77 0.73 0.014 0.009 0.26 0.24 0.14 0.12 0.01 0.1 0.3 0.32 0.31 0.39 0.33 0.087 0.17 0.02 0.13 050g04 mo-001 sc-501-14 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 14 1 8 7 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. dip14: plastic dual in-line package; 14 leads (300 mil) sot27-1
hef4013b_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 20 february 2013 11 of 16 nxp semiconductors hef4013b-q100 dual d-type flip-flop fig 11. package outline sot108-1 (so14) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot108-1 x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 7 8 1 14 y 076e06 ms-012 pin 1 index 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.35 0.34 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 99-12-27 03-02-19 0 2.5 5 mm scale so14: plastic small outline package; 14 leads; body width 3.9 mm sot108-1
hef4013b_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 20 february 2013 12 of 16 nxp semiconductors hef4013b-q100 dual d-type flip-flop fig 12. package outline sot402-1 (tssop14) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot402-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 17 14 8 a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 a max. 1.1 pin 1 index
hef4013b_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 20 february 2013 13 of 16 nxp semiconductors hef4013b-q100 dual d-type flip-flop 15. abbreviations 16. revision history table 11. abbreviations acronym description hbm human body model esd electrostatic discharge mm machine model mil military table 12. revision history document id release date data sheet status change notice supersedes hef4013b_q100 v.2 20130220 product data sheet - hef4013b_q100 modifications: ? HEF4013BP-Q100 (dip14) added. hef4013b_q100 v.1 20120807 product data sheet - -
hef4013b_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 20 february 2013 14 of 16 nxp semiconductors hef4013b-q100 dual d-type flip-flop 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 17.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 17.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qualified for use in automotive applications. unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
hef4013b_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 20 february 2013 15 of 16 nxp semiconductors hef4013b-q100 dual d-type flip-flop no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any licens e under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 17.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors hef4013b-q100 dual d-type flip-flop ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 20 february 2013 document identifier: hef4013b_q100 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 functional description . . . . . . . . . . . . . . . . . . . 4 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 recommended operating conditions. . . . . . . . 5 10 static characteristics. . . . . . . . . . . . . . . . . . . . . 5 11 dynamic characteristics . . . . . . . . . . . . . . . . . . 6 12 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 application information. . . . . . . . . . . . . . . . . . . 9 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 17 legal information. . . . . . . . . . . . . . . . . . . . . . . 14 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 17.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 18 contact information. . . . . . . . . . . . . . . . . . . . . 15 19 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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